EP2S15F672C3 Altera, EP2S15F672C3 Datasheet - Page 24

IC STRATIX II FPGA 15K 672-FBGA

EP2S15F672C3

Manufacturer Part Number
EP2S15F672C3
Description
IC STRATIX II FPGA 15K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S15F672C3

Number Of Logic Elements/cells
15600
Number Of Labs/clbs
780
Total Ram Bits
419328
Number Of I /o
366
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1879
EP2S15F672C3

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S15F672C3
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S15F672C3
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2S15F672C3
Manufacturer:
ALTERA
0
Part Number:
EP2S15F672C3N
Manufacturer:
ALTERA
Quantity:
500
Part Number:
EP2S15F672C3N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2S15F672C3N
Manufacturer:
ALTERA
0
Adaptive Logic Modules
2–16
Stratix II Device Handbook, Volume 1
Figure 2–12. Conditional Operation Example
The arithmetic mode also offers clock enable, counter enable,
synchronous up/down control, add/subtract control, synchronous clear,
synchronous load. The LAB local interconnect data inputs generate the
clock enable, counter enable, synchronous up/down and add/subtract
control signals. These control signals are good candidates for the inputs
that are shared between the four LUTs in the ALM. The synchronous clear
and synchronous load options are LAB-wide signals that affect all
registers in the LAB. The Quartus II software automatically places any
registers that are not used by the counter into other LABs.
Carry Chain
The carry chain provides a fast carry function between the dedicated
adders in arithmetic or shared arithmetic mode. Carry chains can begin in
either the first ALM or the fifth ALM in an LAB. The final carry-out signal
is routed to an ALM, where it is fed to local, row, or column interconnects.
Carry Chain
syncdata
X[0]
X[1]
X[2]
Y[0]
Y[1]
Y[2]
ALM 1
ALM 2
Comb &
Comb &
Comb &
Comb &
Adder
Adder
Adder
Adder
Logic
Logic
Logic
Logic
X[2]
X[0]
X[1]
Adder output
is not used.
syncload
syncload
syncload
D
D
D
reg0
reg1
reg0
carry_out
Q
Q
Q
R[0]
R[1]
R[2]
Altera Corporation
To general or
local routing
To general or
local routing
To general or
local routing
To local routing &
then to LAB-wide
syncload
May 2007

Related parts for EP2S15F672C3