EP2S60F672C4N Altera, EP2S60F672C4N Datasheet - Page 27

• Manufacturer Part Number: EP2S60F672C4N
• Description: IC STRATIX II FPGA 60K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F672C4N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 492
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 492
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1913; EP2S60F672C4N

Figure 2–14. Example of a 3-bit Add Utilizing Shared Arithmetic Mode
Altera Corporation
May 2007
3-Bit Add Example
implemented in adders.
implemented in LUTs.
+
2nd stage add is
1st stage add is
1 1 0 1
1 1 0
+
Binary Add
1 1 0
1 0 1
0 1 0
0 0 1
+
C2 C1 C0
R3 R2 R1 R0
Shared Arithmetic Chain
In addition to the dedicated carry chain routing, the shared arithmetic
chain available in shared arithmetic mode allows the ALM to implement
a three-input add. This significantly reduces the resources necessary to
implement large adder trees or correlator functions.
The shared arithmetic chains can begin in either the first or fifth ALM in
an LAB. The Quartus II Compiler creates shared arithmetic chains longer
than 16 (8 ALMs in arithmetic or shared arithmetic mode) by linking
LABs together automatically. For enhanced fitting, a long shared
+
+
Equivalents
Decimal
X2 X1 X0
S2 S1 S0
2 x 6
Y2 Y1 Y0
Z2 Z1 Z0
+
13
6
5
2
1
X0
Y0
Z0
X1
Y1
Z1
X2
Y2
Z2
ALM Implementation
ALM 1
ALM 2
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
Stratix II Device Handbook, Volume 1
S0
C0
S1
C1
S2
C2
shared_arith_in = '0'
'0'
carry_in = '0'
Stratix II Architecture
R0
R1
R2
R3
2–19