EP2S60F484C3N Altera, EP2S60F484C3N Datasheet - Page 160

• Manufacturer Part Number: EP2S60F484C3N
• Description: IC STRATIX II FPGA 60K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F484C3N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 334
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 334
• Frequency (max): 816.99MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1906; EP2S60F484C3N

Timing Model
5–24
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
PCI
PCI-X
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL with OCT
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.5-V Differential HSTL Class I
1.5-V Differential HSTL Class II
1.8-V Differential HSTL Class I
1.8-V Differential HSTL Class II
LVDS
HyperTransport
LVPECL
Table 5–34. Output Timing Measurement Methodology for Output Pins
(5)
Input measurement point at internal node is 0.5 × V
Output measuring point for V
Input stimulus edge rate is 0 to V
Less than 50-mV ripple on V
V
(4)
(4)
(4)
CCPD
(5)
(4)
Table
I/O Standard
(4)
= 2.97 V, less than 50-mV ripple on V
5–34:
CCIO
MEAS
R
S
CC
and V
50
25
50
50
25
50
50
25
25
25
25
25
50
50
25
(Ω)
at buffer output is 0.5 × V
in 0.2 ns (internal signal) from the driver preceding the I/O buffer.
CCPD
R
CCIO
, V
D
100
100
100
(Ω)
CCINT
and V
Loading and Termination
CCINT
= 1.15 V with less than 30-mV ripple
CCPD
R
T
.
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
(Ω)
, V
CCIO
CCINT
.
V
CCIO
3.135
3.135
2.375
1.710
1.425
2.970
2.970
2.325
2.325
1.660
1.660
1.660
1.660
1.375
1.375
1.140
2.325
2.325
1.660
1.660
1.375
1.375
1.660
1.660
2.325
2.325
3.135
= 1.15 V
(V)
V
Notes
1.123
1.123
0.790
0.790
0.790
0.790
0.648
0.648
1.123
1.123
0.790
0.790
0.648
0.648
0.790
0.790
TT
(V)
(1), (2),
C
L
10
10
(pF)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Altera Corporation
(3)
Measurement
V
1.5675
1.5675
1.1875
0.7125
1.1625
1.1625
0.6875
0.6875
1.1625
1.1625
0.6875
0.6875
1.1625
1.1625
1.5675
MEAS
April 2011
0.855
1.485
1.485
0.570
Point
0.83
0.83
0.83
0.83
0.83
0.83
0.83
0.83
(V)