EP1S60B956C7 Altera, EP1S60B956C7 Datasheet - Page 58
EP1S60B956C7
Manufacturer Part Number
EP1S60B956C7
Description
IC STRATIX FPGA 60K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S60B956C7
Number Of Logic Elements/cells
57120
Number Of Labs/clbs
5712
Total Ram Bits
5215104
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1432
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TriMatrix Memory
2–44
Stratix Device Handbook, Volume 1
Independent Clock Mode
The memory blocks implement independent clock mode for true dual-
port memory. In this mode, a separate clock is available for each port
(ports A and B). Clock A controls all registers on the port A side, while
clock B controls all registers on the port B side. Each port, A and B, also
supports independent clock enables and asynchronous clear signals for
port A and B registers.
independent clock mode.
Figure 2–24
shows a TriMatrix memory block in
Altera Corporation
July 2005
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