XCS40XL-5PQG208C Xilinx Inc, XCS40XL-5PQG208C Datasheet - Page 19
![IC SPARTAN-XL FPGA 40K 208-PQFP](/photos/6/71/67100/pq208_sml.jpg)
XCS40XL-5PQG208C
Manufacturer Part Number
XCS40XL-5PQG208C
Description
IC SPARTAN-XL FPGA 40K 208-PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-XLr
Datasheet
1.XCS05XL-4VQG100C.pdf
(83 pages)
Specifications of XCS40XL-5PQG208C
Number Of Logic Elements/cells
1862
Number Of Labs/clbs
784
Total Ram Bits
25088
Number Of I /o
169
Number Of Gates
40000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1301
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XCS40XL-5PQG208C
Manufacturer:
XILINX
Quantity:
656
Part Number:
XCS40XL-5PQG208C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
3-State Long Line Drivers
A pair of 3-state buffers is associated with each CLB in the
array. These 3-state buffers (BUFT) can be used to drive
signals onto the nearest horizontal longlines above and
below the CLB. They can therefore be used to implement
multiplexed or bidirectional buses on the horizontal lon-
glines, saving logic resources.
There is a weak keeper at each end of these two horizontal
longlines. This circuit prevents undefined floating levels.
However, it is overridden by any driver.
The buffer enable is an active High 3-state (i.e., an active
Low enable), as shown in
DS060 (v1.8) June 26, 2008
Product Specification
G4
G1
F2
F1
F3
"Weak Keeper"
M
R
~100 kΩ
M
M
Table
0
11.
Figure 17: Detail of Spartan/XL Dedicated Carry Logic
Figure 18: 3-state Buffers Implement a Multiplexer
1
D
A
A
BUFT
Z = (D
www.xilinx.com
D
A
B
B
• A) + (D
M
I
Three-State Buffer Example
Figure 18
ment a multiplexer. The selection is accomplished by the
buffer 3-state signal.
Pay particular attention to the polarity of the T pin when
using these buffers in a design. Active High 3-state (T) is
identical to an active Low output enable, as shown in
Table
Table 11: Three-State Buffer Functionality
BUFT
1
0
3
1
0
B
1
0
M
M
M
Spartan and Spartan-XL FPGA Families Data Sheet
• B) + (D
11.
IN
IN
X
0
shows how to use the 3-state buffers to imple-
C
D
OUT
0
C
C
C
1
• C) + (D
C
1
C IN
OUT0
BUFT
N
G2
G3
• N)
F4
T
1
0
D
N
M
M
M
N
BUFT
TO
FUNCTION
GENERATORS
DS060_17_080400
DS060_18_080400
OUT
IN
Z
19