XC3190A-3PC84C Xilinx Inc, XC3190A-3PC84C Datasheet - Page 29
![IC LOGIC CL ARRAY 9000GAT 84PLCC](/photos/6/73/67346/xc3190a-3pc84c_sml.jpg)
XC3190A-3PC84C
Manufacturer Part Number
XC3190A-3PC84C
Description
IC LOGIC CL ARRAY 9000GAT 84PLCC
Manufacturer
Xilinx Inc
Series
XC3000A/Lr
Datasheet
1.XC3190A-3PC84C.pdf
(76 pages)
Specifications of XC3190A-3PC84C
Number Of Labs/clbs
320
Total Ram Bits
64160
Number Of I /o
70
Number Of Gates
6000
Voltage - Supply
4.25 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
84-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Logic Elements/cells
-
Other names
122-1046
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3190A-3PC84C
Manufacturer:
XILINX
Quantity:
1 831
Part Number:
XC3190A-3PC84C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input(s) of the FPGA(s). The serial configuration bitstream
must be available at the DIN input of the lead FPGA a short
set-up time before each rising CCLK edge. The lead device
then presents the preamble data (and all data that over-
Figure 29: Slave Serial Mode Circuit Diagram
November 9, 1998 (Version 3.1)
R
RESET
Product Obsolete or Under Obsolescence
Computer
Micro
Port
I/O
STRB
D0
D1
D2
D3
D4
D5
D6
D7
+5 V
+5 V
XC3000 Series Field Programmable Gate Arrays
CCLK
DIN
INIT
RESET
M0
flows the lead device) on its DOUT pin. There is an internal
delay of 0.5 CCLK periods, which means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy-chain accepts data on the subsequent rising
CCLK edge.
D/P
*
M1
FPGA
PWRDWN
I/O Pins
Other
DOUT
HDC
LDC
M2
5 k
General-
Purpose
User I/O
Pins
*
Optional
Daisy-Chained
LCAs with
Different
Configurations
Activated, a
5-k Resistor is
Required in
Series with M1
If Readback is
X5993
7-31
7