XC4005-5PQ208C Xilinx Inc, XC4005-5PQ208C Datasheet - Page 4
![IC LOGIC CL ARRAY 5000GAT 208PQ](/photos/28/18/281824/xc4005-5pq208c_sml.jpg)
XC4005-5PQ208C
Manufacturer Part Number
XC4005-5PQ208C
Description
IC LOGIC CL ARRAY 5000GAT 208PQ
Manufacturer
Xilinx Inc
Series
XC4000r
Datasheet
1.XC4003-6PQ100C.pdf
(40 pages)
Specifications of XC4005-5PQ208C
Number Of Logic Elements/cells
466
Number Of Labs/clbs
196
Total Ram Bits
6272
Number Of I /o
112
Number Of Gates
5000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1069
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
G4
G3
G2
G1
F4
F3
F2
F1
XC4000, XC4000A, XC4000H Logic Cell Array Families
Figure 1. Simplified Block Diagram of XC4000-Families Configurable Logic Block
independently for each of the two registers; this input also
can be disabled for either flip-flop. A separate global Set/
Reset line (not shown in Figure 1) sets or clears each
register during power-up, reconfiguration, or when a dedi-
cated Reset net is driven active. This Reset net does not
compete with other routing resources; it can be connected
to any package pin as a global reset input.
Each flip-flop can be triggered on either the rising or falling
clock edge. The source of a flip-flop data input is program-
mable: it is driven either by the functions F', G', and H', or
the Direct In (DIN) block input . The flip-flops drive the XQ
and YQ CLB outputs.
In addition, each CLB F' and G' function generator con-
tains dedicated arithmetic logic for the fast generation of
carry and borrow signals, greatly increasing the efficiency
K
(CLOCK)
FUNCTION
FUNCTION
LOGIC
LOGIC
G1-G4
F1-F4
OF
OF
G'
F'
FUNCTION
LOGIC
F', G',
AND
OF
H1
H'
H1
C1
DIN
F'
G'
H'
G'
H'
H'
F'
DIN
F'
G'
H'
DIN
C2
2-10
C3
S/R
and performance of adders, subtracters, accumulators,
comparators and even counters.
Multiplexers in the CLB map the four control inputs, la-
beled C1 through C4 in Figure 1, into the four internal
control signals (H1, DIN, S/R, and EC) in any arbitrary
manner.
The flexibility and symmetry of the CLB architecture facili-
tates the placement and routing of a given application.
Since the function generators and flip-flops have inde-
pendent inputs and outputs, each can be treated as a
separate entity during placement to achieve high packing
density. Inputs, outputs, and the functions themselves can
freely swap positions within a CLB to avoid routing conges-
tion during the placement and routing operation.
C4
EC
MULTIPLEXER CONTROLLED
BY CONFIGURATUON PROGRAM
1
1
CONTROL
CONTROL
S/R
S/R
D
EC
D
EC
SD
RD
SD
RD
X6099
Q
Q
BYPASS
BYPASS
XQ
YQ
Y
X