AT40K05AL-1BQU Atmel, AT40K05AL-1BQU Datasheet - Page 16
![FPGA 5K GATE 3.3V 1NS 144-LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT40K05AL-1BQU
Manufacturer Part Number
AT40K05AL-1BQU
Description
FPGA 5K GATE 3.3V 1NS 144-LQFP
Manufacturer
Atmel
Series
AT40KALr
Datasheet
1.AT40K05AL-1AQC.pdf
(55 pages)
Specifications of AT40K05AL-1BQU
Number Of Logic Elements/cells
256
Total Ram Bits
2048
Number Of I /o
114
Number Of Gates
10000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Labs/clbs
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Set/Reset Scheme
The AT40KAL family reset scheme is essentially the same as the clock scheme except
that there is only one Global Reset. A dedicated Global Set/Reset bus can be driven by
any User I/O, except those used for clocking (Global Clocks or Fast Clocks). The auto-
matic placement tool will choose the reset net with the most connections to use the
global resources. You can change this by using an RSBUF component in your design to
indicate the global reset. Additional resets will use the express bus network.
The Global Set/Reset is distributed to each column of the array. Like Sector Clock mux,
there is Sector Set/Reset mux at every four cells. Each sector column of four cells is
set/reset by a Plane 5 express bus or Global Set/Reset using the Sector Set/Reset mux,
see Figure 11 on page 17. The set/reset provided to each sector column of four cells is
either inverted or non-inverted using the Sector Reset mux.
The function of the Set/Reset input of a register is determined by a configuration bit in
each cell. The Set/Reset input of a register is active low (logic 0) by default. Setting or
Resetting of a register is asynchronous. Before configuration on power-up, a logic 1 (a
high) is provided by each register (i.e., all registers are set at power-up).
AT40KAL Series FPGA
16
2818F–FPGA–07/06