EP1C3T100C8 Altera, EP1C3T100C8 Datasheet - Page 47
![IC CYCLONE FPGA 2910 LE 100-TQFP](/photos/6/70/67055/544-100-tqfp_sml.jpg)
EP1C3T100C8
Manufacturer Part Number
EP1C3T100C8
Description
IC CYCLONE FPGA 2910 LE 100-TQFP
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C3T100C8
Number Of Logic Elements/cells
2910
Number Of Labs/clbs
291
Total Ram Bits
59904
Number Of I /o
65
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1016
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C3T100C8
Manufacturer:
ALTERA
Quantity:
4
Company:
Part Number:
EP1C3T100C8
Manufacturer:
ALTERA
Quantity:
241
Part Number:
EP1C3T100C8
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1C3T100C8N
Manufacturer:
ALTERA44
Quantity:
55
Part Number:
EP1C3T100C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–28. Row I/O Block Connection to the Interconnect
Notes to
(1)
(2)
Altera Corporation
May 2008
The 21 data and control signals consist of three data out lines, io_dataout[2..0], three output enables,
io_coe[2..0], three input clock enables, io_cce_in[2..0], three output clock enables, io_cce_out[2..0],
three clocks, io_cclk[2..0], three asynchronous clear signals, io_caclr[2..0], and three synchronous clear
signals, io_csclr[2..0].
Each of the three IOEs in the row I/O block can have one io_datain input (combinatorial or registered) and one
comb_io_datain (combinatorial) input.
LAB Local
Interconnect
Figure
R4 Interconnects
to Adjacent LAB
Interconnect
Direct Link
2–28:
LAB
io_datain[2..0] and
comb_io_datain[2..0] (2)
C4 Interconnects
from Adjacent LAB
Interconnect
Direct Link
I/O Block Local
Interconnect
io_clk[5:0]
21
I/O Block
Row I/O Block
Contains up to
Row
Three IOEs
21 Data and
Control Signals
from Logic Array (1)
I/O Structure
Preliminary
2–41