EP4CE6E22C8N Altera, EP4CE6E22C8N Datasheet - Page 32

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EP4CE6E22C8N

Manufacturer Part Number
EP4CE6E22C8N
Description
IC CYCLONE IV FPGA 6K 144EQFP
Manufacturer
Altera
Series
CYCLONE® IV Er

Specifications of EP4CE6E22C8N

Number Of Logic Elements/cells
6272
Number Of Labs/clbs
392
Total Ram Bits
270000
Number Of I /o
91
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-EQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

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1–32
Table 1–36. LVDS Receiver Timing Specifications for Cyclone IV Devices
Cyclone IV Device Handbook, Volume 3
f
clock
frequency)
HSIODR
SW
Input jitter
tolerance
t
Notes to
(1) Cyclone IV E—LVDS receiver is supported at all I/O Banks.
(2) t
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8,
HSCLK
LOCK
Symbol
(2)
Cyclone IV GX—LVDS receiver is supported at I/O Banks 3, 4, 5, 6, 7, 8, and 9.
I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
(input
LOCK
Table
is the time required for the PLL to lock from the end-of-device configuration.
1–36:
Modes
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
Min
100
10
10
10
10
10
10
80
70
40
20
10
C6
437.5
437.5
437.5
437.5
437.5
437.5
437.5
Max
875
875
875
875
875
400
500
1
Min
100
10
10
10
10
10
10
80
70
40
20
10
C7, I7
402.5
402.5
Max
370
370
370
370
370
740
740
740
740
740
400
500
1
Min
100
10
10
10
10
10
10
80
70
40
20
10
C8, A7
(Note
402.5
402.5
Max
320
320
320
320
320
640
640
640
640
640
400
550
1
1),
(3)
—Preliminary
Min
100
Chapter 1: Cyclone IV Device Datasheet
10
10
10
10
10
10
80
70
40
20
10
C8L, I8L
© December 2010 Altera Corporation
Max
320
320
320
320
320
362
640
640
640
640
640
362
550
600
1
Switching Characteristics
Min
100
10
10
10
10
10
10
80
70
40
20
10
C9L
Max
250
250
250
250
250
265
500
500
500
500
500
265
640
700
1
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
ps
ps

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