EPF6010ATC100-3 Altera, EPF6010ATC100-3 Datasheet - Page 3

• Manufacturer Part Number: EPF6010ATC100-3
• Description: IC FLEX 6000 FPGA 10K 100-TQFP
• Manufacturer: Altera
• Series: FLEX 6000r

Specifications of EPF6010ATC100-3

• Number Of Logic Elements/cells: 880
• Number Of Labs/clbs: 88
• Number Of I /o: 71
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Other names: 544-1271

General
Description
Note:
(1)
Altera Corporation
Table 3. FLEX 6000 Device Performance for Common Designs
16-bit loadable counter
16-bit accumulator
24-bit accumulator
16-to-1 multiplexer (pin-to-pin)
16 × 16 multiplier with a 4-stage pipeline
This performance value is measured as a pin-to-pin delay.
Application
The Altera
a low-cost alternative to high-volume gate array designs. FLEX 6000
devices are based on the OptiFLEX architecture, which minimizes die size
while maintaining high performance and routability. The devices have
reconfigurable SRAM elements, which give designers the flexibility to
quickly change their designs during prototyping and design testing.
Designers can also change functionality during operation via in-circuit
reconfiguration.
FLEX 6000 devices are reprogrammable, and they are 100% tested prior to
shipment. As a result, designers are not required to generate test vectors
for fault coverage purposes, allowing them to focus on simulation and
design verification. In addition, the designer does not need to manage
inventories of different gate array designs. FLEX 6000 devices are
configured on the board for the specific functionality required.
Table 3
performance values shown were obtained using Synopsys DesignWare or
LPM functions. Special design techniques are not required to implement
the applications; the designer simply infers or instantiates a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
(1)
shows FLEX 6000 performance for some common designs. All
®
FLEX 6000 programmable logic device (PLD) family provides
LEs Used
FLEX 6000 Programmable Logic Device Family Data Sheet
592
16
16
24
10
-1 Speed
Grade
12.1
172
172
136
84
Performance
-2 Speed
Grade
13.4
153
153
123
67
-3 Speed
Grade
16.6
133
108
133
58
Units
MHz
MHz
MHz
MHz
ns
3