EP1C6T144C6N Altera, EP1C6T144C6N Datasheet - Page 24
![IC CYCLONE FPGA 5980 LE 144-TQFP](/photos/6/70/67061/544-144-tqfp_sml.jpg)
EP1C6T144C6N
Manufacturer Part Number
EP1C6T144C6N
Description
IC CYCLONE FPGA 5980 LE 144-TQFP
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C6T144C6N
Number Of Logic Elements/cells
5980
Number Of Labs/clbs
598
Total Ram Bits
92160
Number Of I /o
98
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1815
EP1C6T144C6N
EP1C6T144C6N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C6T144C6N
Manufacturer:
ALTERA
Quantity:
5
Company:
Part Number:
EP1C6T144C6N
Manufacturer:
ALTERA
Quantity:
885
Part Number:
EP1C6T144C6N
Manufacturer:
ALTERA
Quantity:
20 000
Cyclone Device Handbook, Volume 1
Embedded
Memory
2–18
Preliminary
The Cyclone embedded memory consists of columns of M4K memory
blocks. EP1C3 and EP1C6 devices have one column of M4K blocks, while
EP1C12 and EP1C20 devices have two columns (refer to
page 1–1
various types of memory with or without parity, including true dual-port,
simple dual-port, and single-port RAM, ROM, and FIFO buffers. The
M4K blocks support the following features:
■
■
■
■
■
■
■
■
■
■
■
1
Memory Modes
The M4K memory blocks include input registers that synchronize writes
and output registers to pipeline designs and improve system
performance. M4K blocks offer a true dual-port mode to support any
combination of two-port operations: two reads, two writes, or one read
and one write at two different clock frequencies.
dual-port memory.
Figure 2–12. True Dual-Port Memory Configuration
4,608 RAM bits
250 MHz performance
True dual-port memory
Simple dual-port memory
Single-port memory
Byte enable
Parity bits
Shift register
FIFO buffer
ROM
Mixed clock mode
Violating the setup or hold time on the address registers could
corrupt the memory contents. This applies to both read and
write operations.
for total RAM bits per density). Each M4K block can implement
data
address
wren
clocken
q
aclr
A
clock
[ ]
A
A
A
[ ]
A
A
A
[ ]
A
B
address
clocken
clock
data
wren
Figure 2–12
aclr
q
B
B
B
B
[ ]
[ ]
[ ]
B
B
B
Altera Corporation
Table 1–1 on
shows true
May 2008