EP3C5F256I7 Altera, EP3C5F256I7 Datasheet - Page 34

• Manufacturer Part Number: EP3C5F256I7
• Description: IC CYCLONE III FPGA 5K 256 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5F256I7

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Page 34
Chip-Wide Reset
Register Power-Up Level
If the purpose of turning off the clock is to stop clocking registers to prevent the
register output change, you can control the input to the register instead, as illustrated
in
keeps toggling. This ensures the register output is synchronized with other register
outputs that use the same clock. Gating the clock to the register introduces additional
delay to the clock and the register output may not be synchronized with other signals.
Figure 6. Synchronous Clock Enable
If you must implement gated clocks using logic resources, register the gating signal
that enables or disables the clock to filter out any glitches that might appear in the
gating signal. Otherwise, glitches from the gating signal can propagate to the clock
signal. Also, gating the clock signal at the source minimizes the clock delay
differences between different blocks within the design that are clocked by the same
clock signal.
A Cyclone III device supports the chip-wide reset that clears all registers in the device,
including registers of the M9K blocks. This reset overrides all other control signals of
the registers and allows you to re-initialize the device at any given time.
To enable the chip-wide reset from the Quartus II software, on the Assignments menu,
click Settings. Under Device, click Device & Pin Options. Then, on the General
window, turn on Enable device-wide reset (DEV_CLRn). Enable this feature before
compiling your design. When the chip-wide reset option is turned on, holding the
DEV_CLRn pin low resets all the registers. When this feature is turned off, the
DEV_CLRn pin functions as a normal user I/O pin.
You can select the power-up level of the registers in the Cyclone III to be either high or
low. By default, when the device powers up, all registers in the device are cleared and
the registered output signals drive low. Setting the register to power up high prevents
the activation of another device’s active-low input when the Cyclone III device is
powered up. The register power-up high feature can also be used as a system reset
signal when the Cyclone III device is powered up. If a register is set to power-up high,
the register output will remain high until the asynchronous clear signal is asserted or
a low data signal is clocked in. You can use the asynchronous preset signal to ensure
that the register output remains high after the device is powered up. Set the register in
the Quartus II design to power up high before design compilation.
In the Quartus II integrated synthesis, you can apply the Power-Up Level logic option
in the Assignment Editor, with a Tcl assignment, or create an altera_attribute
assignment in your source code.
Figure
6. The enable signal controls the input to the register, while the clock signal
Data
Enable
D
Q
© November 2008 Altera Corporation
Design and Compilation