EP4CE10E22C8LN Altera, EP4CE10E22C8LN Datasheet - Page 417

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EP4CE10E22C8LN

Manufacturer Part Number
EP4CE10E22C8LN
Description
IC CYCLONE IV FPGA 10K 144EQFP
Manufacturer
Altera
Series
CYCLONE® IV Er

Specifications of EP4CE10E22C8LN

Number Of Logic Elements/cells
10320
Number Of Labs/clbs
645
Total Ram Bits
414000
Number Of I /o
91
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-EQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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0
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0
Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
Figure 3–11. Option 1 for Transmitter Core Clocking (Channel Reconfiguration Mode)
© December 2010 Altera Corporation
FPGA Fabric
tx_clkout[0]
Low-speed parallel clock (tx_clkout0)
High-speed serial clock generated by the MPLL
Figure 3–11
channels of a transceiver block.
Option 2: Use the Respective Channel Transmitter Core Clocks
Enable this option if you want the individual transmitter channel tx_clkout
signals to provide the write clock to their respective Transmit Phase Compensation
FIFOs.
This option is typically enabled when each transceiver channel is reconfigured to a
different functional mode using channel reconfiguration.
shows the sharing of channel 0’s tx_clkout between all four regular
Transceiver Block
RX0
RX1
RX2
RX3
TX0
TX1
TX2
TX3
Cyclone IV Device Handbook, Volume 2
MPLL
3–27

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