EP1C6Q240I7N Altera, EP1C6Q240I7N Datasheet - Page 27

• Manufacturer Part Number: EP1C6Q240I7N
• Description: IC CYCLONE FPGA 5980 LE 240-PQFP
• Manufacturer: Altera
• Series: Cyclone®r

Specifications of EP1C6Q240I7N

• Number Of Logic Elements/cells: 5980
• Number Of Labs/clbs: 598
• Total Ram Bits: 92160
• Number Of I /o: 185
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 240-MQFP, 240-PQFP
• Family Name: Cyclone®
• Number Of Logic Blocks/elements: 5980
• # I/os (max): 185
• Frequency (max): 320.1MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 5980
• Ram Bits: 92160
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1814; EP1C6Q240I7N

Figure 2–14. Shift Register Memory Configuration
Altera Corporation
May 2008
w
w
w
w
w × m × n Shift Register
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
register outputs (number of taps n × width w) must be less than the
maximum data width of the M4K RAM block (×36). To create larger shift
registers, multiple memory blocks are cascaded together.
Data is written into each address location at the falling edge of the clock
and read from the address at the rising edge of the clock. The shift register
mode logic automatically controls the positive and negative edge
clocking to shift the data in one clock cycle.
memory block in the shift register mode.
Memory Configuration Sizes
The memory address depths and output widths can be configured as
4,096 × 1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or 256 × 18
bits), and 128 × 32 (or 128 × 36 bits). The 128 × 32- or 36-bit configuration
Figure 2–14
w
w
w
w
Embedded Memory
shows the M4K
n Number
of Taps
Preliminary
2–21