EP1K50FC484-3N Altera, EP1K50FC484-3N Datasheet - Page 83
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EP1K50FC484-3N
Manufacturer Part Number
EP1K50FC484-3N
Description
IC ACEX 1K FPGA 50K 484-FBGA
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet
1.EP1K10TC100-3N.pdf
(86 pages)
Specifications of EP1K50FC484-3N
Number Of Logic Elements/cells
2880
Number Of Labs/clbs
360
Total Ram Bits
40960
Number Of I /o
249
Number Of Gates
199000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
484-FBGA
Family Name
ACEX™ 1K
Number Of Usable Gates
50000
Number Of Logic Blocks/elements
2880
# I/os (max)
249
Frequency (max)
166.67MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
2880
Ram Bits
40960
Device System Gates
199000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1K50FC484-3N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1K50FC484-3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
Figure 31. ACEX 1K I
Configuration &
Operation
EP1K30
I
Current (mA)
CC
Supply
100
80
60
40
20
0
CCACTIVE
The ACEX 1K architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
configuration schemes.
Operating Modes
The ACEX 1K architecture uses SRAM configuration elements that
require configuration data to be loaded every time the circuit powers up.
The process of physically loading the SRAM data into the device is called
configuration. Before configuration, as V
Power-On Reset (POR). This POR event clears the device and prepares it
for configuration. The ACEX 1K POR time does not exceed 50 s.
1
vs. Operating Frequency
EP1K100
I
Current (mA)
Frequency (MHz)
CC
Supply
50
When configuring with a configuration device, refer to the
relevant configuration device data sheet for POR timing
information.
300
200
100
0
100
ACEX 1K Programmable Logic Device Family Data Sheet
Frequency (MHz)
EP1K50
I
Current (mA)
CC
Supply
50
200
150
100
50
CC
0
100
rises, the device initiates a
Frequency (MHz)
50
100
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