EP1K50FC484-2N Altera, EP1K50FC484-2N Datasheet - Page 24
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EP1K50FC484-2N
Manufacturer Part Number
EP1K50FC484-2N
Description
IC ACEX 1K FPGA 50K 484-FBGA
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet
1.EP1K10TC100-3N.pdf
(86 pages)
Specifications of EP1K50FC484-2N
Number Of Logic Elements/cells
2880
Number Of Labs/clbs
360
Total Ram Bits
40960
Number Of I /o
249
Number Of Gates
199000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
484-FBGA
Family Name
ACEX™ 1K
Number Of Usable Gates
50000
Number Of Logic Blocks/elements
2880
# I/os (max)
249
Frequency (max)
200MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
2880
Ram Bits
40960
Device System Gates
199000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1K50FC484-2N
Manufacturer:
ALTERA
Quantity:
3 000
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 12. ACEX 1K LE Clear & Preset Modes
24
Asynchronous Load with Clear
Asynchronous Load with Preset
Asynchronous Clear
Chip-Wide Reset
Chip-Wide Reset
(Asynchronous
(Asynchronous
labctrl1 or
(Preset)
labctrl2
labctrl2
labctrl1
labctrl2
(Clear)
labctrl1
(Data)
(Data)
Load)
data3
data3
Load)
NOT
NOT
D
CLRN
VCC
PRN
NOT
NOT
In addition to the six clear and preset modes, ACEX 1K devices provide a
chip-wide reset pin that can reset all registers in the device. Use of this
feature is set during design entry. In any of the clear and preset modes, the
chip-wide reset overrides all other signals. Registers with asynchronous
presets may be preset when the chip-wide reset is asserted. Inversion can
be used to implement the asynchronous preset.
of how to setup the preset and clear inputs for the desired functionality.
Q
Chip-Wide Reset
Chip-Wide Reset
Asynchronous Preset
labctrl1 or
labctrl2
D
CLRN
PRN
VCC
Q
D
CLRN
(Asynchronous
D
PRN
Asynchronous Load without Clear or Preset
CLRN
PRN
Q
Q
labctrl1
(Data)
Load)
data3
Chip-Wide Reset
Asynchronous Preset & Clear
Chip-Wide Reset
NOT
NOT
labctrl2
labctrl1
Figure 12
Altera Corporation
D
shows examples
CLRN
PRN
Q
D
CLRN
PRN
Q