EPF6024AQC240-2 Altera, EPF6024AQC240-2 Datasheet - Page 36
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EPF6024AQC240-2
Manufacturer Part Number
EPF6024AQC240-2
Description
IC FLEX 6000 FPGA 24K 240-PQFP
Manufacturer
Altera
Series
FLEX 6000r
Datasheet
1.EPF6010ATC100-3N.pdf
(52 pages)
Specifications of EPF6024AQC240-2
Number Of Logic Elements/cells
1960
Number Of Labs/clbs
196
Number Of I /o
199
Number Of Gates
24000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Other names
544-1286
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF6024AQC240-2
Manufacturer:
ALTERA
Quantity:
1 150
Part Number:
EPF6024AQC240-2
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
FLEX 6000 Programmable Logic Device Family Data Sheet
Timing Model
36
The continuous, high-performance FastTrack Interconnect routing
resources ensure predictable performance and accurate simulation and
timing analysis. This predictable performance contrasts with that of
FPGAs, which use a segmented connection scheme and therefore have
unpredictable performance.
Device performance can be estimated by following the signal path from a
source, through the interconnect, to the destination. For example, the
registered performance between two LEs on the same row can be
calculated by adding the following parameters:
■
■
■
■
The routing delay depends on the placement of the source and destination
LEs. A more complex registered path may involve multiple combinatorial
LEs between the source and destination LEs.
Timing simulation and delay prediction are available with the Simulator
and Timing Analyzer, or with industry-standard EDA tools. The
Simulator offers both pre-synthesis functional simulation to evaluate logic
design accuracy and post-synthesis timing simulation with 0.1-ns
resolution. The Timing Analyzer provides point-to-point timing delay
information, setup and hold time analysis, and device-wide performance
analysis.
Figure 19
routing paths to and from the various elements of the FLEX 6000 device.
LE register clock-to-output delay (t
Routing delay (t
LE LUT delay (t
LE register setup time (t
shows the overall timing model, which maps the possible
DATA_TO_REG
ROW +
t
LOCAL
SU
)
)
)
CO +
t
REG_TO_OUT
Altera Corporation
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