EPF10K20RC208-4N Altera, EPF10K20RC208-4N Datasheet - Page 62

• Manufacturer Part Number: EPF10K20RC208-4N
• Description: IC FLEX 10K FPGA 20K 208-RQFP
• Manufacturer: Altera
• Series: FLEX-10K®r

Specifications of EPF10K20RC208-4N

• Number Of Logic Elements/cells: 1152
• Number Of Labs/clbs: 144
• Total Ram Bits: 12288
• Number Of I /o: 147
• Number Of Gates: 63000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-RQFP
• Family Name: FLEX 10K
• Number Of Usable Gates: 20000
• Number Of Logic Blocks/elements: 1152
• # I/os (max): 147
• Frequency (max): 125MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 5V
• Logic Cells: 1152
• Ram Bits: 12288
• Device System Gates: 63000
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: RQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2210

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FLEX 10K Embedded Programmable Logic Device Family Data Sheet
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
EABAA
EABRCCOMB
EABRCREG
EABWP
EABWCCOMB
EABWCREG
EABDD
EABDATACO
EABDATASU
EABDATAH
EABWESU
EABWEH
EABWDSU
EABWDH
EABWASU
EABWAH
EABWO
Table 35. EAB Timing Macroparameters
Symbol
EAB address access delay
EAB asynchronous read cycle time
EAB synchronous read cycle time
EAB write pulse width
EAB asynchronous write cycle time
EAB synchronous write cycle time
EAB data-in to data-out valid delay
EAB clock-to-output delay when using output registers
EAB data/address setup time before clock when using input register
EAB data/address hold time after clock when using input register
EAB WE setup time before clock when using input register
EAB WE hold time after clock when using input register
EAB data setup time before falling edge of write pulse when not using input
registers
EAB data hold time after falling edge of write pulse when not using input
registers
EAB address setup time before rising edge of write pulse when not using
input registers
EAB address hold time after falling edge of write pulse when not using input
registers
EAB write enable to data output valid delay
Notes
Parameter
(1),
(6)
Altera Corporation
Conditions