EP3C40F780C8N Altera, EP3C40F780C8N Datasheet - Page 63
![IC CYCLONE III FPGA 40K 780FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP3C40F780C8N
Manufacturer Part Number
EP3C40F780C8N
Description
IC CYCLONE III FPGA 40K 780FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C40F780C8N.pdf
(274 pages)
Specifications of EP3C40F780C8N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1161216
Number Of I /o
535
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
39600
# I/os (max)
535
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
39600
Ram Bits
1161216
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2504
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C40F780C8N
Manufacturer:
ALTERA
Quantity:
364
Design Checklist
© November 2008 Altera Corporation
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If you are using third-party synthesis tools to synthesize your design, use the netlist
generated by the synthesis tools for the Quartus II Fitter to do the place-and-route
procedure.
Use synchronous design. Use a single clock source to clock the registers in your design.
Register your combinational logic outputs and inputs to filter out glitches.
Pay attention to the clocks in your design. Use clock pins, the global clock network, clock
control blocks, and the PLL for your clock signals.
Chip-wide reset can be used to clear the registers.
If you need the registers to be powered up high, set the register power-up level.
Use the Quartus II Design Assistant to check design reliability.
Use incremental compilation to preserve results and performance of unchanged logic in
your design, achieve timing closure more efficiently and reduce compilation time when you
make changes to your design, especially for bottom-up or top-down design flow.
Take advantage of the various Quartus II software settings to optimize power consumption,
including the Design Space Explorer, power-driven compilation, gate-level register retiming,
minimum area-synthesis, and Power Optimization Advisor.
Split large designs into smaller partitions and register the partition I/O boundary.
Separate the source code of each block into different files.
Allocate the resources among the design partitions to avoid conflict.
Use the Quartus II Chip Planner to create a design floorplan using LogicLock region
assignments.
Pay attention to the design techniques to optimize power consumption, including clock
power management, memory power reduction, pipelining and retiming, and architectural
optimization.
Use the Quartus II Pin Planner to create and edit pin related assignments.
Use the Pin Planner Package View to visually identify the locations of the pins, I/O banks,
V
Use the Pin Migration View in the Pin Planner to identify the pins that change functions
between migration devices.
Use the correct current strength and slew rate on output or bidirectional pins to prevent
signal overshoot or undershoot for signal noise reduction, or to prevent stair-step output
from the pins.
Use the Cyclone III series on-chip termination feature for I/O impedance matching and
saving board space.
Use the programmable pre-emphasis for high-frequency signals to reduce attenuation to
high-frequency signals during transmission.
Use the dedicated differential output buffers to implement the differential I/O standards
without requiring additional resistors.
Determine the location of the PLL you want to use based on the location of the clock pins
your design uses, or let the Quartus II software determine the PLL location based on your
pin assignment for the clock pins.
Assign the ports of the altpll megafunction and the altpll_reconfig megafunction to the
recommended pins.
Perform timing or functional simulation on your PLL design to check the functionality.
Use the
R EF
groups, and the differential pin pairing.
CLKUSR
pin to control the initialization upon the completion of the configuration.
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