EP4CE40F29I7N Altera, EP4CE40F29I7N Datasheet - Page 38

• Manufacturer Part Number: EP4CE40F29I7N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29I7N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 39600
• Logic Cells: 39600
• Ram Bits: 1161216
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–38
Glossary
Table 1–46. Glossary (Part 1 of 5)
Cyclone IV Device Handbook, Volume 3
Letter
M
D
G
H
N
O
A
B
C
E
F
J
K
L
I
f
GCLK
GCLK PLL
HSIODR
Input Waveforms
for the SSTL
Differential I/O
Standard
JTAG Waveform
HSCLK
Term
—
—
—
—
—
—
—
—
—
—
Table 1–46
Captured
V
High-speed I/O block: High-speed receiver/transmitter input and output clock frequency.
Input pin directly to Global Clock network.
Input pin to Global Clock network through the PLL.
High-speed I/O block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).
SWING
Driven
Signal
Signal
to be
to be
TMS
TDO
TCK
TDI
lists the glossary for this chapter.
t
JCH
t
t
JSZX
JPZX
t
JCP
t
JSSU
t
JCL
t
JSH
t
t
JPCO
JSCO
t
t
JPSU_TDI
JPSU_TMS
Definitions
—
—
—
—
—
—
—
—
—
—
t
JSXZ
t
JPH
Chapter 1: Cyclone IV Device Datasheet
© December 2010 Altera Corporation
t
JPXZ
V
V
V
REF
IH
IL
Glossary