EP20K60EQC240-1 Altera, EP20K60EQC240-1 Datasheet - Page 33
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EP20K60EQC240-1
Manufacturer Part Number
EP20K60EQC240-1
Description
IC APEX 20KE FPGA 600K 240PQFP
Manufacturer
Altera
Series
APEX-20K®r
Datasheet
1.EP20K30ETC144-3.pdf
(117 pages)
Specifications of EP20K60EQC240-1
Number Of Logic Elements/cells
2560
Number Of Labs/clbs
2560
Total Ram Bits
32768
Number Of I /o
151
Number Of Gates
162000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Altera Corporation
Figure 21. ESB in Input/Output Clock Mode
Notes to
(1)
(2)
All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset.
APEX 20KE devices have four dedicated clocks.
Figure
wraddress[ ]
rdaddress[ ]
outclock
outclken
inclken
inclock
data[ ]
Dedicated Clocks
21:
wren
rden
(2)
2 or 4
Dedicated Inputs &
Global Signals
Input/Output Clock Mode
The input/output clock mode contains two clocks. One clock controls all
registers for inputs into the ESB: data input, WE, RE, read address, and
write address. The other clock controls the ESB data output registers. The
ESB also supports clock enable and asynchronous clear signals; these
signals also control the reading and writing of registers independently.
Input/output clock mode is commonly used for applications where the
reads and writes occur at the same system frequency, but require different
clock enable signals for the input and output registers.
the ESB in input/output clock mode.
Single-Port Mode
The APEX 20K ESB also supports a single-port mode, which is used when
simultaneous reads and writes are not required. See
4
Note (1)
D
ENA
D
ENA
D
ENA
APEX 20K Programmable Logic Device Family Data Sheet
Q
Q
Q
D
ENA
D
ENA
Generator
Pulse
Write
Q
Q
Data In
Read Address
Write Address
Read Enable
Write Enable
RAM/ROM
1,024 × 2
2,048 × 1
Data Out
128 × 16
256 × 8
512 × 4
Figure
D
ENA
Figure 21
Q
22.
shows
to MegaLAB,
FastTrack &
Local
Interconnect
33