EPF10K30EQC208-1X Altera, EPF10K30EQC208-1X Datasheet - Page 20

• Manufacturer Part Number: EPF10K30EQC208-1X
• Description: IC FLEX 10KE FPGA 30K 208-PQFP
• Manufacturer: Altera
• Series: FLEX-10KE®r

Specifications of EPF10K30EQC208-1X

• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 216
• Total Ram Bits: 24576
• Number Of I /o: 147
• Number Of Gates: 119000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 10. FLEX 10KE Cascade Chain Operation
20
d[(4n – 1)..(4n – 4)]
AND Cascade Chain
d[3..0]
d[7..4]
LUT
LUT
LUT
Cascade Chain
With the cascade chain, the FLEX 10KE architecture can implement
functions that have a very wide fan-in. Adjacent LUTs can be used to
compute portions of the function in parallel; the cascade chain serially
connects the intermediate values. The cascade chain can use a logical AND
or logical OR (via De Morgan’s inversion) to connect the outputs of
adjacent LEs. An a delay as low as 0.6 ns per LE, each additional LE
provides four more inputs to the effective width of a function. Cascade
chain logic can be created automatically by the Altera Compiler during
design processing, or manually by the designer during design entry.
Cascade chains longer than eight bits are implemented automatically by
linking several LABs together. For easier routing, a long cascade chain
skips every other LAB in a row. A cascade chain longer than one LAB
skips either from even-numbered LAB to even-numbered LAB, or from
odd-numbered LAB to odd-numbered LAB (e.g., the last LE of the first
LAB in a row cascades to the first LE of the third LAB). The cascade chain
does not cross the center of the row (e.g., in the EPF10K50E device, the
cascade chain stops at the eighteenth LAB and a new one begins at the
nineteenth LAB). This break is due to the EAB’s placement in the middle
of the row.
Figure 10
form functions with a wide fan-in. These examples show functions of
4n variables implemented with n LEs. The LE delay is 0.9 ns; the cascade
chain delay is 0.6 ns. With the cascade chain, 2.7 ns are needed to decode
a 16-bit address.
shows how the cascade function can connect adjacent LEs to
LEn
LE1
LE2
d[(4n – 1)..(4n – 4)]
OR Cascade Chain
d[3..0]
d[7..4]
LUT
LUT
LUT
Altera Corporation
LEn
LE1
LE2