EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 2

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Page 2
Table 1. Known Issues for Cyclone IV Devices (Part 2 of 2)
Human Body Model Electrostatic Discharge
DisplayPort Receiver Specification
Errata Sheet for Cyclone IV Devices
“Quartus II Mapping Issue with a PCIe ×1 Interface Using
the Hard IP Block”
The Quartus II software incorrectly maps the PCIe
interfaces when using the hard IP block.
“PLL Cascading for Transceiver Applications is not
Supported”
Only the direct REFCLK or DIFFCLK pins driving the
phase-locked loop (PLL) input of a transceiver are
allowed.
“Removal of the ±500 PPM and ±1000 PPM Options for
the Programmable PPM Detector in the ALTGX
MegaWizard Plug-In Manager”
The ±500 PPM and ±1000 PPM options in the ALTGX
MegaWizard Plug-In Manager are not supported.
“External Memory Specification for DDR2 SDRAM”
Final full-rate DDR2 SDRAM maximum clock rate
specification on column and row I/Os.
The row I/Os on certain Cyclone IV GX devices do not meet the human body model
(HBM) electrostatic discharge (ESD) specification stated in the device datasheet. All
other I/Os, including the high-speed serial interface (HSSI) I/Os, meet the HBM ESD
specification.
This issue only affects the EP4CGX15 and EP4CGX30 (except for the F484 package)
devices and there will not be a silicon fix.
The EP4CGX15 and EP4CGX30 (except for the F484 package) devices are considered
HBM Class 0 per JEDEC standard 22-A114. Altera recommends handling the
ESD-sensitive devices using the ESD control methods as stated in ANSI/ESD S20.20
or IEC61340-5-1.
If you have additional questions, contact your local Altera
The Cyclone IV GX transceiver meets the transmitter compliance specifications as a
1.62 Gbps and 2.7 Gbps transmitter for a digital display interface unit.
However, the Cyclone IV GX transceiver does not meet the receiver jitter tolerance
specification that requires tracking of at least one unit interval (UI) at 2 MHz jitter
tolerance test without asynchronous spread spectrum clocking (SSC) modulation
enabled. If you want to use the transceiver as a DisplayPort receiver, you must verify
the system margin and its jitter components in the application design.
Issue
All Cyclone IV E Core Voltage
All Cyclone IV GX Devices
All Cyclone IV GX Devices
All Cyclone IV GX Devices
Affected Devices
1.0-V I8L Devices
Human Body Model Electrostatic Discharge
®
sales representative.
For the solution, refer to
March 2011 Altera Corporation
Specification for DDR2
version 10.1 and later.
No plan to fix silicon.
SDRAM” on page
Quartus II software
Quartus II software
“External Memory
Planned Fix
version 10.1
9.