EP4CE55F23I7 Altera, EP4CE55F23I7 Datasheet - Page 9
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EP4CE55F23I7
Manufacturer Part Number
EP4CE55F23I7
Description
IC CYCLONE IV FPGA 55K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F23I7
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Quantity
Price
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External Memory Specification for DDR2 SDRAM
External Memory Specification for DDR2 SDRAM
Table 5. Full-Rate DDR2 SDRAM Support for Cyclone IV E Core Voltage 1.0-V Devices
March 2011 Altera Corporation
DDR2 SDRAM
Note to
(1) You must use the 267-MHz memory device speed grade to achieve the maximum clock rate.
Table
Memory Standard
5:
In the Quartus II software version 10.0, the Cyclone IV E I8L speed grade supported
full-rate DDR2 SDRAM with a maximum clock rate of up to 150 MHz on column and
row I/Os. This maximum clock rate is a preliminary specification pending the
finalization of the timing model.
In the Quartus II software version 10.0 SP1 and later, the Cyclone IV E I8L speed
grade full-rate DDR2 SDRAM maximum clock rate specification on column and row
I/Os has been revised due to the finalization of the timing model for the Cyclone IV E
device family.
Designs that already use the affected devices running full-rate DDR2 SDRAM at the
old maximum clock rate and pass timing in the Quartus II software version 10.0 SP1
and later run acceptably at the old frequencies—provided that the board settings
panel in the IP MegaWizard Plug-In Manager is populated accurately and the board
trace models representative of the relevant system are correctly entered in the
Pin Planner.
Core Voltage
Cyclone IV E
Table 5
Device
1.0 V
lists the current specification.
Speed Grade
I8L
Maximum Clock Rate (MHz)
Column and Row I/O
Single Chip Select
133
Errata Sheet for Cyclone IV Devices
(1)
Page 9