EP4CE55F29I8L Altera, EP4CE55F29I8L Datasheet - Page 41
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EP4CE55F29I8L
Manufacturer Part Number
EP4CE55F29I8L
Description
IC CYCLONE IV FPGA 55K 780FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F29I8L
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
374
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Chapter 3: Memory Blocks in Cyclone IV Devices
Overview
© November 2009 Altera Corporation
Figure 3–2. Cyclone IV Devices Address Clock Enable Block Diagram
The address clock enable is typically used to improve the effectiveness of cache
memory applications during a cache-miss. The default value for the address clock
enable signals is low.
Figure 3–3
write cycles, respectively.
Figure 3–3. Cyclone IV Devices Address Clock Enable During Read Cycle Waveform
latched address
(inside memory)
addressstall
q (asynch)
rdaddress
q (synch)
inclock
and
rden
Figure 3–4
doutn-1
doutn
addressstall
an
address[N]
address[0]
a0
clock
doutn
show the address clock enable waveform during read and
a0
dout0
a1
dout0
dout1
a2
address[N]
address[0]
register
register
dout1
a1
dout1
a3
dout1
dout1
Cyclone IV Device Handbook, Volume 1
address[0]
address[N]
a4
dout1
a4
dout4
a5
dout4
a5
dout5
a6
3–5
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