EP4CE55F29I8L Altera, EP4CE55F29I8L Datasheet - Page 34
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EP4CE55F29I8L
Manufacturer Part Number
EP4CE55F29I8L
Description
IC CYCLONE IV FPGA 55K 780FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F29I8L
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
374
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
1–34
Table 1–40. IOE Programmable Delay on Column Pins for Cyclone IV E 1.0 V Core Voltage Devices
Table 1–41. IOE Programmable Delay on Row Pins for Cyclone IV E 1.0 V Core Voltage Devices
Cyclone IV Device Handbook, Volume 3
—Preliminary
Input delay from pin to
internal cells
Input delay from pin to
input register
Delay from output register
to output pin
Input delay from
dual-purpose clock pin to
fan-out destinations
Notes to
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
Input delay from pin to
internal cells
Input delay from pin to
input register
Delay from output register
to output pin
Input delay from
dual-purpose clock pin to
fan-out destinations
Notes to
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
software.
Table
Table
Parameter
Parameter
1–40:
1–41:
IOE Programmable Delay
Table 1–40
core voltage devices.
Pad to I/O
dataout to core
Pad to I/O input
register
I/O output
register to pad
Pad to global
clock network
Pad to I/O
dataout to core
Pad to I/O input
register
I/O output
register to pad
Pad to global
clock network
Paths Affected
Paths Affected
and
Table 1–41
Number
Number
Setting
Setting
12
12
of
of
7
8
2
7
8
2
list the IOE programmable delay for Cyclone IV E 1.0 V
Offset
Offset
Min
Min
0
0
0
0
0
0
0
0
2.054
2.010
0.641
0.971
2.057
2.059
0.670
0.960
C8L
C8L
Fast Corner
Fast Corner
1.924
1.875
0.631
0.931
1.921
1.919
0.623
0.919
I8L
I8L
Max Offset
Max Offset
Chapter 1: Cyclone IV Device Datasheet
3.387
3.341
1.111
1.684
3.389
3.420
1.160
1.656
© December 2010 Altera Corporation
C8L
C8L
(Note
Slow Corner
Slow Corner
(Note
4.146
4.374
1.420
2.258
4.017
4.252
1.377
2.298
C9L
C9L
1), (2)—Preliminary
Switching Characteristics
1),
(2)
3.411
3.367
1.124
1.684
3.412
3.441
1.168
1.656
I8L
I8L
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns