EP20K200EQC240-2 Altera, EP20K200EQC240-2 Datasheet - Page 31
![IC APEX 20KE FPGA 200K 240-PQFP](/photos/6/72/67260/544-240-pqfp_sml.jpg)
EP20K200EQC240-2
Manufacturer Part Number
EP20K200EQC240-2
Description
IC APEX 20KE FPGA 200K 240-PQFP
Manufacturer
Altera
Series
APEX-20K®r
Datasheet
1.EP20K30ETC144-3.pdf
(117 pages)
Specifications of EP20K200EQC240-2
Number Of Logic Elements/cells
8320
Number Of Labs/clbs
832
Total Ram Bits
81920
Number Of I /o
168
Number Of Gates
404000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP20K200EQC240-2
Manufacturer:
ALTERA
Quantity:
43
Company:
Part Number:
EP20K200EQC240-2
Manufacturer:
ALTERA
Quantity:
5
Company:
Part Number:
EP20K200EQC240-2X
Manufacturer:
ALTERA
Quantity:
885
Part Number:
EP20K200EQC240-2X
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Altera Corporation
Figure 18. Deep Memory Block Implemented with Multiple ESBs
The ESB implements two forms of dual-port memory: read/write clock
mode and input/output clock mode. The ESB can also be used for
bidirectional, dual-port memory applications in which two ports read or
write simultaneously. To implement this type of dual-port memory, two
or four ESBs are used to support two simultaneous reads or writes. This
functionality is shown in
Figure 19. APEX 20K ESB Implementing Dual-Port RAM
Clock A
APEX 20K Programmable Logic Device Family Data Sheet
ESB
ESB
ESB
Address Decoder
address_a[]
data_a[]
we_a
clkena_a
Figure
Port A
19.
address_b[]
clkena_b
Port B
data_b[]
we_b
to System Logic
Clock B
31