EP1SGX10CF672C7 Altera, EP1SGX10CF672C7 Datasheet - Page 214
![IC STRATIX GX FPGA 10KLE 672FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP1SGX10CF672C7
Manufacturer Part Number
EP1SGX10CF672C7
Description
IC STRATIX GX FPGA 10KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX10CF672C7
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
362
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Operating Conditions
Figure 6–1. Receiver Input Waveforms for Differential I/O Standards
6–12
Stratix GX Device Handbook, Volume 1
Note to
(1)
V
Table 6–12. 1.5-V I/O Specifications (Part 2 of 2)
OL
Symbol
Drive strength is programmable according to values in found in the Stratix GX Architecture chapter of the
Stratix GX Device Handbook, Volume 1.
Tables 6–8
Single-Ended Waveform
Differential Waveform
Low-level output voltage
through 6–12:
Parameter
V
CM
Figures 6–1
waveforms, respectively, for all differential I/O standards (LVDS, 3.3-V
PCML, LVPECL, and HyperTransport technology).
V
ID
through
V
ID
I
OL
(V ID (Differential) = 2 x V ID (single-ended))
= 2 mA
6–3
Conditions
show receiver input and transmitter output
(1)
V
ID
Minimum
p − n = 0 V
Positive Channel (p) = V
Negative Channel (n) = V
Ground
0.25
Maximum
Altera Corporation
×
V
CCIO
OH
OL
June 2006
Units
V
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