EP2C70F672C6 Altera, EP2C70F672C6 Datasheet - Page 53
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EP2C70F672C6
Manufacturer Part Number
EP2C70F672C6
Description
IC CYCLONE II FPGA 70K 672-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C70F672C6
Number Of Logic Elements/cells
68416
Number Of Labs/clbs
4276
Total Ram Bits
1152000
Number Of I /o
422
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-5°C ~ 50°C
Package / Case
672-FBGA
For Use With
P0304 - DE2-70 CALL FOR ACADEMIC PRICING544-1703 - VIDEO KIT W/CYCLONE II EP2C70N544-1699 - DSP KIT W/CYCLONE II EPS2C70N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-2140
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C70F672C6
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP2C70F672C6N
Manufacturer:
ALTERA
Quantity:
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Figure 2–23. Signal Path Through the I/O Block
Altera Corporation
February 2007
From Logic
To Logic
Array
Array
Row or Column
io_cce_out
io_clk[5..0]
io_dataout
io_datain0
io_datain1
io_cce_in
io_caclr
io_csclr
io_cclk
io_coe
The pin’s datain signals can drive the logic array. The logic array drives
the control and data signals, providing a flexible routing resource. The
row or column IOE clocks, io_clk[5..0], provide a dedicated routing
resource for low-skew, high-speed clocks. The global clock network
generates the IOE clocks that feed the row or column I/O regions (see
“Global Clock Network & Phase-Locked Loops” on page
Figure 2–23
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset,
clk_in, and clk_out.
selection.
Data and
Selection
Control
Signal
illustrates the signal paths through the I/O block.
oe
ce_in
ce_out
aclr/preset
sclr/preset
clk_in
clk_out
dataout
Figure 2–24
To Other
IOEs
Cyclone II Device Handbook, Volume 1
illustrates the control signal
IOE
Cyclone II Architecture
2–16).
2–41