EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 7

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Quartus II Mapping Issue with a PCIe ×1 Interface Using the Hard IP Block
Quartus II Mapping Issue with a PCIe ×1 Interface Using the Hard IP
Block
PLL Cascading for Transceiver Applications is not Supported
Removal of the ±500 PPM and ±1000 PPM Options for the
Programmable PPM Detector in the ALTGX MegaWizard Plug-In
Manager
March 2011 Altera Corporation
f
Table 4
Table 4. Quartus II Software Planned Support
The
guidelines for transceiver applications that run at ≥ 2.97 Gbps data rate.
The Quartus II software version 10.0 SP1 and prior releases incorrectly allowed logical
channel 0 to be placed in any physical channel for the PCIe Gen1 × 1 interface with the
hard IP block. For correct operation with the hard IP block, logical channel 0 must be
placed in physical channel 0.
This issue is fixed in the Quartus II software version 10.1. If you have already
designed or fabricated your boards using the incorrect mapping, file a service request
using
Using the clock output of another PLL to drive the PLL input of a transceiver is not
allowed. Only the direct REFCLK or DIFFCLK pins driving the PLL input of a transceiver
is allowed.
Hence, PLL cascading for transceiver applications is restricted by the Quartus II
software version 10.1 and later. If you use PLL cascading for transceiver applications,
the Quartus II Analysis and Synthesis reports an error during compilation.
The ±500 PPM and ±1000 PPM options for the Programmable PPM Detector feature in
the ALTGX MegaWizard
supported in the Quartus II software version 10.0 SP1 and later. These options are
removed because the programmed PPM threshold values exceed the receiver CDR
PPM tolerance between the upstream transmitter reference clock and the local
receiver reference clock.
Releases prior to version 11.0
Version 11.0 release and later
Quartus II Software Version
Cyclone IV Device Family Pin Connection Guidelines
mysupport
lists the Quartus II software support planning.
for assistance to remedy this issue.
™
Plug-In Manager, as shown in
Follow the guidelines documented in this errata sheet as the
Quartus II software does not enforce these guidelines.
The Quartus II software enforces the guidelines documented in
this errata sheet.
Software Enforcement Plan
has been updated with the
Figure
Errata Sheet for Cyclone IV Devices
1, are no longer
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