EPF10K100EFC484-1 Altera, EPF10K100EFC484-1 Datasheet - Page 55
![IC FLEX 10KE FPGA 100K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EPF10K100EFC484-1
Manufacturer Part Number
EPF10K100EFC484-1
Description
IC FLEX 10KE FPGA 100K 484-FBGA
Manufacturer
Altera
Series
FLEX-10KE®r
Datasheet
1.EPF10K30ETC144-3.pdf
(100 pages)
Specifications of EPF10K100EFC484-1
Number Of Logic Elements/cells
4992
Number Of Labs/clbs
624
Total Ram Bits
49152
Number Of I /o
338
Number Of Gates
257000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
FLEX 10KE
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4992
# Registers
338
# I/os (max)
338
Frequency (max)
333.33MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
4992
Ram Bits
49152
Device System Gates
257000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1935
EPF10K100EFC484-1
EPF10K100EFC484-1
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K100EFC484-1
Manufacturer:
UNISONIC
Quantity:
9 000
Company:
Part Number:
EPF10K100EFC484-1N
Manufacturer:
AVAGO
Quantity:
11 350
Altera Corporation
Figure 26. FLEX 10KE Device IOE Timing Model
Figure 27. FLEX 10KE Device EAB Timing Model
Output Register
Input Register
Data Feedback
into FastTrack
Interconnect
Output Enable
Address
Clock Enable
Data-In
Clock
Clock
WE
RE
Data-In
Clock
Clear
EAB Data Input
Write Enable
Input Delays
Read Enable
Input Delays
EAB Clock
t
t
t
t
t
t
t
EABDATA1
EABDATA2
EABWE1
EABWE2
EABRE1
EABRE2
EABCLK
Delays
Delay
Feedback Delay
Contol Delay
Output Data
I/O Element
I/O Register
Input Delay
t
INCOMB
Delay
t
t
t
IOC
IOFD
IOD
Input Register
t
t
t
t
t
t
EABCO
EABBYPASS
EABSU
EABH
EABCH
EABCL
Delays
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Input Register Delay
Block Delays
RAM/ROM
t
t
t
t
t
t
t
t
t
t
t
AA
DD
WP
WDSU
WDH
WASU
WAH
WO
RP
RASU
RAH
I/O Register
t
t
t
t
t
Delays
IOCO
IOCOMB
IOSU
IOH
IOCLR
t
INREG
Output Register
t
t
t
t
t
t
EABCO
EABBYPASS
EABSU
EABH
EABCH
EABCL
Delays
Delays
Output
t
t
t
t
t
t
t
OD1
OD2
OD3
XZ
ZX1
ZX2
ZX3
EAB Output
t
EABOUT
Delay
Data-Out
55