EP4CGX150CF23I7 Altera, EP4CGX150CF23I7 Datasheet - Page 474
EP4CGX150CF23I7
Manufacturer Part Number
EP4CGX150CF23I7
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX150CF23I7
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP4CGX15BN11C8N PDF datasheet
- EP4CGX15BN11C8N PDF datasheet #2
- EP4CGX15BN11C8N PDF datasheet #3
- EP4CGX15BN11C8N PDF datasheet #4
- Current page: 474 of 478
- Download datasheet (13Mb)
1–40
Table 1–46. Glossary (Part 3 of 5)
Cyclone IV Device Handbook, Volume 3
Letter
S
T
Single-ended
voltage-
referenced I/O
Standard
SW (Sampling
Window)
t
Channel-to-
channel-skew
(TCCS)
tcin
t
tcout
t
t
t
Timing Unit
Interval (TUI)
t
t
t
tpllcin
tpllcout
C
CO
DUTY
FALL
H
INJITTER
OUTJITTER_DEDCLK
OUTJITTER_IO
Term
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver
changes to the new logic state. The new logic state is then maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing.
High-speed I/O block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling window.
High-speed receiver and transmitter input and output clock period.
High-speed I/O block: The timing difference between the fastest and slowest output edges,
including t
Delay from the clock pad to the I/O input register.
Delay from the clock pad to the I/O output.
Delay from the clock pad to the I/O output register.
High-speed I/O block: Duty cycle on high-speed transmitter output clock.
Signal high-to-low transition time (80–20%).
Input register hold time.
High-speed I/O block: The timing budget allowed for skew, propagation delays, and data sampling
window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t
Period jitter on the PLL clock input.
Period jitter on the dedicated clock output driven by a PLL.
Period jitter on the general purpose I/O driven by a PLL.
Delay from the PLL inclk pad to the I/O input register.
Delay from the PLL inclk pad to the I/O output register.
V
V
CO
OH
OL
variation and clock skew. The clock is included in the TCCS measurement.
Definitions
V
REF
Chapter 1: Cyclone IV Device Datasheet
© December 2010 Altera Corporation
V
V
IH(DC)
IL(DC)
C
/w).
V
V
IH ( AC )
IL(AC )
V
CCIO
V
Glossary
SS
Related parts for EP4CGX150CF23I7
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: