EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 76

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–74
Table 1–58. DLL Frequency Range Specifications for Arria II GZ Devices (Part 2 of 2)
Table 1–61. Memory Output Clock Jitter Specification for Arria II GX Devices
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Note to
(1) Low indicates a 6-bit DQS delay setting; high indicates a 5-bit DQS delay setting.
Clock period jitter
Cycle-to-cycle period
jitter
Frequency Mode
Parameter
Table
7
1–58:
Table 1–59
Table 1–59. DQS Phase Offset Delay Per Setting for Arria II GX Devices
Table 1–60
Table 1–60. DQS Phase Shift Error Specification for DLL-Delayed Clock (t
Devices
Table 1–61
Notes to
(1) The valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes
(2) The typical value equals the average of the minimum and maximum values.
(3) The delay settings are linear.
Note to
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay
Network
470-630
Number of DQS Delay Buffer
Global
Global
Clock
4 to 5.
buffers in a 3 speed grade is ± 78 ps or ± 39 ps.
Frequency Range (MHz)
–3
Table
Table
(Note 1)
Speed Grade
lists the DQS phase offset delay per stage for Arria II GX devices.
lists the DQS phase shift error for Arria II GZ devices.
lists the memory output clock jitter specifications for Arria II GX devices.
I3, C5, I5
1–60:
1–59:
C4
C6
Symbol
1
2
3
4
t
t
JIT(per)
JIT(cc)
470-590
–4
-100
-200
Min
–4
Max
100
200
Available Phase Shift
60°, 120°, 180°, 240°
Min
7.0
7.0
8.5
112
–3
28
56
84
-125
-250
Min
(Note
Chapter 1: Device Datasheet for Arria II Devices
–5
Max
1), (2),
125
250
Max
13.0
15.0
18.0
December 2010 Altera Corporation
120
–4
30
60
90
Buffer Mode
(3)
DQS Delay
-125
-250
Min
(Note
DQS_PSERR
(Part 1 of 2)
High
(1)
Switching Characteristics
–6
1), (2),
) for Arria II GZ
Max
125
250
Unit
Number of
ps
ps
ps
(3)
Chains
Unit
Delay
ps
ps
ps
ps
6
Unit
ps
ps