EP3C120F484I7 Altera, EP3C120F484I7 Datasheet - Page 28
![IC CYCLONE III FPGA 120K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C120F484I7
Manufacturer Part Number
EP3C120F484I7
Description
IC CYCLONE III FPGA 120K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C120F484I7.pdf
(274 pages)
Specifications of EP3C120F484I7
Number Of Logic Elements/cells
119088
Number Of Labs/clbs
7443
Total Ram Bits
3981312
Number Of I /o
283
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
119088
# I/os (max)
283
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
119088
Ram Bits
3981312
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
For Use With
544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C120F484I7
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP3C120F484I7
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP3C120F484I7N
Manufacturer:
DALLAS
Quantity:
101
Company:
Part Number:
EP3C120F484I7N
Manufacturer:
ALTERA
Quantity:
561
Part Number:
EP3C120F484I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP3C120F484I7N WWW.YIBEIIC.COM
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
1–28
Table 1–39. Glossary (Part 2 of 5)
Cyclone III Device Handbook, Volume 2
Letter
M
N
O
Q
K
L
P
J
JTAG Waveform
PLL Block
Term
—
—
—
—
—
—
Captured
The following block diagram highlights the PLL Specification parameters.
Core Clock
Driven
Signal
Signal
to be
to be
Key
TMS
CLK
TDO
TCK
TDI
Reconfigurable in User Mode
t
JCH
t
t
JSZX
JPZX
t
JCP
t
JSSU
t
JCL
Switchover
f
IN
t
JSH
N
t
t
JPCO
JSCO
t
t
f
INPFD
JPSU_TDI
JPSU_TMS
Definitions
PFD
—
—
—
—
—
—
M
CP
t
JSXZ
t
JPH
Phase tap
LF
Chapter 1: Cyclone III Device Data Sheet
VCO
© January 2010 Altera Corporation
t
JPXZ
f
VCO
Counters
C0..C4
CLKOUT Pins
f
f
OUT _EXT
OUT
Glossary
GCLK