EP1S25B672C7N Altera, EP1S25B672C7N Datasheet - Page 147

• Manufacturer Part Number: EP1S25B672C7N
• Description: IC STRATIX FPGA 25K LE 672-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S25B672C7N

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 473
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
July 2005
780-pin
FineLine
BGA
956-pin
BGA
1,020-pin
FineLine
BGA
780-pin
FineLine
BGA
Table 2–38. EP1S30 Differential Channels
Table 2–39. EP1S40 Differential Channels (Part 1 of 2)
Package
Package
Transmitter/
Transmitter
(4)
Receiver
Transmitter
(4)
Receiver
Transmitter
(4)
Receiver
Transmitter
(4)
Receiver
Transmitter
/Receiver
Receiver
70
66
80
80
80 (2)
80 (2)
Channels
68
66
Channels
The only way you can use the rx_data_align is if one of the following
is true:
■
■
Total
Total
(7)
(7)
The receiver PLL is only clocking receive channels (no resources for
the transmitter)
If all channels can fit in one I/O bank
840
840
840
840
840
840
840
840
840
840
840
840
840
840
840
840
Maximum
Maximum
(Mbps)
Speed
(Mbps)
Speed
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
Note (1)
,
,
(8)
(8)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
(1)
(1)
18
34
17
33
18
35
17
33
19
39
20
40
19
39
20
40
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
Center Fast PLLs
Center Fast PLLs
Note (1)
(1)
17
35
16
33
20
39
20
40
20
39
20
40
16
34
16
33
(1)
16
34
16
33
17
35
16
33
20
39
20
40
20
39
20
40
Stratix Device Handbook, Volume 1
(1)
(1)
18
35
17
33
19
39
20
40
19
39
20
40
18
34
17
33
19 (1)
19 (1)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
20
20
19
19
20
20
Corner Fast PLLs (2),
Corner Fast PLLs (2),
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
20
20
20
20
20
20
20
20
Stratix Architecture
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
20
20
20
20
20
20
20
20
(6)
(6)
(6)
(6)
19 (1)
19 (1)
2–133
(3)
(6)
(6)
(6)
(6)
20
20
19
19
20
20
(3)