EPF10K130EFC484-1 Altera, EPF10K130EFC484-1 Datasheet - Page 61
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EPF10K130EFC484-1
Manufacturer Part Number
EPF10K130EFC484-1
Description
IC FLEX 10KE FPGA 130K 484-FBGA
Manufacturer
Altera
Series
FLEX-10KE®r
Datasheet
1.EPF10K30ETC144-3.pdf
(100 pages)
Specifications of EPF10K130EFC484-1
Number Of Logic Elements/cells
6656
Number Of Labs/clbs
832
Total Ram Bits
65536
Number Of I /o
369
Number Of Gates
342000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-2205
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K130EFC484-1
Manufacturer:
ALTERA
Quantity:
7 973
Altera Corporation
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local
t
t
t
t
t
t
INSUBIDIR
INHBIDIR
INH
OUTCOBIDIR
XZBIDIR
ZXBIDIR
Table 30. External Bidirectional Timing Parameters
Symbol
Microparameters are timing delays contributed by individual architectural elements. These parameters cannot be
measured explicitly.
Operating conditions: VCCIO = 3.3 V ±10% for commercial or industrial use.
Operating conditions: VCCIO = 2.5 V ±5% for commercial or industrial use in EPF10K30E, EPF10K50S,
EPF10K100E, EPF10K130E, and EPF10K200S devices.
Operating conditions: VCCIO = 3.3 V.
Because the RAM in the EAB is self-timed, this parameter can be ignored when the WE signal is registered.
EAB macroparameters are internal parameters that can simplify predicting the behavior of an EAB at its boundary;
these parameters are calculated by summing selected microparameters.
These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing
analysis are required to determine actual worst-case performance.
Contact Altera Applications for test circuit specifications and test conditions.
This timing parameter is sample-tested only.
Bus Specification, revision 2.2.
Setup time for bi-directional pins with global clock at same-row or same-
column LE register
Hold time for bidirectional pins with global clock at same-row or same-column
LE register
Hold time with global clock at IOE register
Clock-to-output delay for bidirectional pins with global clock at IOE register
Synchronous IOE output buffer disable delay
Synchronous IOE output buffer enable delay, slow slew rate= off
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Parameter
Note (9)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
Conditions
61