EP1S25F672I7N Altera, EP1S25F672I7N Datasheet - Page 153
![IC STRATIX FPGA 25K LE 672-FBGA](/photos/6/73/67394/ds-672fbga205-2_0_sml.jpg)
EP1S25F672I7N
Manufacturer Part Number
EP1S25F672I7N
Description
IC STRATIX FPGA 25K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F672I7N
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
473
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
25660
# I/os (max)
473
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S25F672I7N
Manufacturer:
ALTERA
Quantity:
624
- Current page: 153 of 276
- Download datasheet (4Mb)
Figure 2–75. Fast PLL & Channel Layout in the EP1S30 to EP1S80 Devices
Notes to
(1)
(2)
(3)
Altera Corporation
July 2005
Wire-bond packages support up to 624 Mbps.
See
There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of
its bank quadrant, those clocked channels support up to 840 Mbps for “high” speed channels and 462 Mbps for
“low” speed channels as labeled in the device pin-outs at www.altera.com.
FPLL7CLK
Transmitter
Transmitter
Transmitter
Transmitter
FPLL8CLK
Table 2–38
Figure
Receiver
Receiver
Receiver
Receiver
CLKIN
CLKIN
2–75:
through
PLL 7
PLL 1
PLL 2
PLL 8
Fast
Fast
Fast
Fast
2–41
for the number of channels each device supports.
(3)
Channels in 20 Rows (2)
Channels in 20 Rows (2)
Channels in 20 Rows (2)
Channels in 20 Rows (2)
Up to 20 Receiver and
Up to 20 Receiver and
Up to 20 Receiver and
Up to 20 Receiver and
20 Transmitter
20 Transmitter
20 Transmitter
20 Transmitter
(3)
Stratix Device Handbook, Volume 1
Note (1)
PLL 10
PLL 4
PLL 3
PLL 9
Fast
Fast
Fast
Fast
Stratix Architecture
FPLL10CLK
Transmitter
Receiver
Transmitter
Receiver
CLKIN
CLKIN
Transmitter
Receiver
Transmitter
Receiver
FPLL9CLK
2–139
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