EP1SGX25CF672C7 Altera, EP1SGX25CF672C7 Datasheet - Page 13
EP1SGX25CF672C7
Manufacturer Part Number
EP1SGX25CF672C7
Description
IC STRATIX GX FPGA 25KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX25CF672C7
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
455
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix GX
Number Of Logic Blocks/elements
25660
# I/os (max)
455
Frequency (max)
4.38597GHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1SGX25CF672C7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 13 of 272
- Download datasheet (3Mb)
Altera Corporation
June 2006
Each Stratix GX transceiver channel consists of a transmitter and receiver.
The transmitter contains the following:
■
■
■
■
■
■
The receiver contains the following:
■
■
■
■
■
■
■
You can set all the Stratix GX transceiver functions through the Quartus II
software. You can set programmable pre-emphasis, programmable
equalizer, and programmable V
transceiver channel is also capable of BIST generation and verification in
addition to various loopback modes.
for the Stratix GX transceiver channel.
Stratix GX transceivers provide physical coding sublayer (PCS) and
physical media attachment (PMA) implementation for protocols such as
10-gigabit XAUI and GIGE. The PCS portion of the transceiver consists of
the logic array interface, 8B/10B encoder/decoder, pattern detector, word
aligner, rate matcher, channel aligner, and the BIST and pseudo-random
binary sequence pattern generator/verifier. The PMA portion of the
transceiver consists of the serializer/deserializer, the CRU, and the I/O
buffers.
Transmitter PLL
Transmitter phase compensation FIFO buffer
Byte serializer
8B/10B encoder
Serializer (parallel to serial converter)
Transmitter output buffer
Input buffer
Clock recovery unit (CRU)
Deserializer
Pattern detector and word aligner
Rate matcher and channel aligner
8B/10B decoder
Receiver logic array interface
OD
dynamically as well. Each Stratix GX
Stratix GX Device Handbook, Volume 1
Figure 2–2
shows the block diagram
Stratix GX Transceivers
2–3
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