EP1AGX90EF1152I6 Altera, EP1AGX90EF1152I6 Datasheet - Page 86

• Manufacturer Part Number: EP1AGX90EF1152I6
• Description: IC ARRIA GX FPGA 90K 1152FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX90EF1152I6

• Number Of Logic Elements/cells: 90220
• Number Of Labs/clbs: 4511
• Total Ram Bits: 4477824
• Number Of I /o: 538
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

2–80
Enhanced PLLs
Figure 2–65. Arria GX Enhanced PLL
Notes to
(1) Each clock source can come from any of the four clock pins that are physically located on the same side of the device as the PLL.
(2) If the feedback input is used, you will lose one (or two, if FBIN is differential) external clock output pin.
(3) Each enhanced PLL has three differential external clock outputs or six single-ended external clock outputs.
(4) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock
Fast PLLs
Arria GX Device Handbook, Volume 1
control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally
generated global signal cannot drive the PLL.
Global or
Regional
Clock
INCLK[3..0]
Figure
2–65:
4
Shaded Portions of the
PLL are Reconfigurable
Arria GX devices contain up to four enhanced PLLs with advanced clock
management features. These features include support for external clock feedback
mode, spread-spectrum clocking, and counter cascading.
diagram of the enhanced PLL.
Arria GX devices contain up to four fast PLLs with high-speed serial interfacing
ability. Fast PLLs offer high-speed outputs to manage the high-speed differential I/O
interfaces.
FBIN
Switchover
Circuitry
Clock
(2)
/n
Figure 2–66
(Note 1)
Phase Frequency
Detector
PFD
shows a diagram of the fast PLL.
Charge
Pump
Lock Detect
& Filter
Spectrum
Spread
/m
Loop
Filter
VCO Phase Selection
Affecting All Outputs
V
Selectable at Each
PLL Output Port
CO
Phase Selection
VCO
8
Post-Scale
Counters
/c0
/c1
/c2
/c3
/c4
/c5
Figure 2–65
From Adjacent PLL
© December 2009 Altera Corporation
6
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
4
8
6
shows a
Global
Clocks
Regional
Clocks
I/O Buffers (3)
to I/O or general
routing