EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 65
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–47. DSP Block Performance Specifications for Arria II GZ Devices
Table 1–48. Embedded Memory Block Performance Specifications for Arria II GX Devices
December 2010 Altera Corporation
Double mode
Notes to
(1) Maximum is for fully pipelined block with Round and Saturation disabled.
(2) Maximum for loopback input registers disabled, Round and Saturation disabled, and pipeline and output registers enabled.
Memory
Logic
Array
Block
(MLAB)
M9K
Block
Memory
Table
Single port 64 × 10
Simple dual-port 32 × 20 single
clock
Simple dual-port 64 × 10 single
clock
Single-port 256 × 36
Single-port 256 × 36, with the
read-during-write option set to
Old Data
Simple dual-port 256 × 36 single
CLK
Single-port 256 × 36 single CLK,
with the read-during-write option
set to Old Data
True dual port 512 × 18 single CLK
True dual-port 512 × 18 single CLK,
with the read-during-write option
set to Old Data
Min Pulse Width (clock high time)
Min Pulse Width (clock low time)
1–47:
Mode
Embedded Memory Block Specifications
Table 1–48
Mode
lists the embedded memory block specifications for Arria II GX devices.
Multipliers
Resources
Number of
Used
1
ALUTs
Resources Used
—
—
0
0
0
0
0
0
0
0
0
Embedded
Memory
—
—
1
1
1
1
1
1
1
1
1
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
440
–3
450
270
428
360
250
360
250
360
250
900
730
I3
(Note 1)
Performance
690
500
500
500
400
280
400
280
400
280
850
C4
Performance
C5,I5
450
450
450
360
250
360
250
360
250
950
770
380
–4
1130
378
378
378
310
210
310
210
310
210
920
C6
MHz
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ps
ps
1–63