EP2S60F672C4 Altera, EP2S60F672C4 Datasheet - Page 40
EP2S60F672C4
Manufacturer Part Number
EP2S60F672C4
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672C4
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1127
EP2S60F672C4ES
EP2S60F672C4ES
Available stocks
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Part Number
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Quantity
Price
Company:
Part Number:
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Manufacturer:
ALTERA
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TriMatrix Memory
Figure 2–20. M512 RAM Block LAB Row Interface
2–32
Stratix II Device Handbook, Volume 1
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
C4 Interconnect
6
M512 RAM Block Local
Interconnect Region
16
M4K RAM Blocks
The M4K RAM block includes support for true dual-port RAM. The M4K
RAM block is used to implement buffers for a wide variety of applications
such as storing processor code, implementing lookup schemes, and
implementing larger memory applications. Each block contains 4,608
RAM bits (including parity bits). M4K RAM blocks can be configured in
the following modes:
■
■
■
■
■
■
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
ROM
Shift register
2
clocks
datain
M512 RAM
LAB Row Clocks
signals
control
Block
address
dataout
Altera Corporation
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
R4 Interconnect
May 2007
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