EP1S30F1020C6N Altera, EP1S30F1020C6N Datasheet - Page 138

no-image

EP1S30F1020C6N

Manufacturer Part Number
EP1S30F1020C6N
Description
IC STRATIX FPGA 30K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F1020C6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
726
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
32470
# I/os (max)
726
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
32470
Ram Bits
3317184
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S30F1020C6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S30F1020C6N
Manufacturer:
ALTERA
Quantity:
5
Part Number:
EP1S30F1020C6N
Manufacturer:
ALTERA
0
Part Number:
EP1S30F1020C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP1S30F1020C6N
0
I/O Structure
2–124
Stratix Device Handbook, Volume 1
f
For more information on I/O standards supported by Stratix devices, see
the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the
Stratix Device Handbook, Volume 2.
Stratix devices contain eight I/O banks in addition to the four enhanced
PLL external clock out banks, as shown in
banks on the right and left of the device contain circuitry to support high-
speed differential I/O for LVDS, LVPECL, 3.3-V PCML, and
HyperTransport inputs and outputs. These banks support all I/O
standards listed in
SSTL-18 Class II, and HSTL Class II outputs. The top and bottom I/O
banks support all single-ended I/O standards. Additionally, Stratix
devices support four enhanced PLL external clock output banks,
allowing clock output capabilities such as differential support for SSTL
and HSTL.
Table 2–32
Table 2–31
shows I/O standard support for each I/O bank.
except PCI I/O pins or PCI-X 1.0, GTL,
Figure
2–70. The four I/O
Altera Corporation
July 2005

Related parts for EP1S30F1020C6N