EP2S60F1020C4 Altera, EP2S60F1020C4 Datasheet - Page 51
EP2S60F1020C4
Manufacturer Part Number
EP2S60F1020C4
Description
IC STRATIX II FPGA 60K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F1020C4
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
718
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1131
EP2S60F1020C4ES
EP2S60F1020C4ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F1020C4
Manufacturer:
ALTERA
Quantity:
1 238
Company:
Part Number:
EP2S60F1020C4
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP2S60F1020C4N
Manufacturer:
ALTERA
Quantity:
3
Part Number:
EP2S60F1020C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–28. DSP Block Diagram for 18 × 18-Bit Configuration
Altera Corporation
May 2007
Optional Serial Shift
Register Outputs to
interface block
Next DSP Block
in the Column
From the row
Register Inputs from
Optional Serial Shift
Previous DSP Block
PRN
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
PRN
PRN
PRN
PRN
PRN
PRN
PRN
Q
Q
Q
Q
Q
Q
Q
Q
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
Saturate
Saturate
Saturate
Saturate
Round/
Round/
Round/
Round/
Q1.15
Q1.15
Q1.15
Q1.15
Multiplier Block
D
ENA
D
ENA
D
ENA
D
ENA
CLRN
CLRN
CLRN
CLRN
PRN
PRN
PRN
PRN
Q
Q
Q
Q
Adder Output Block
Optional Pipline
Register Stage
Accumulator
Accumulator
Optional Stage Configurable
as Accumulator or Dynamic
Subtractor/
Subtractor/
Adder/
Adder/
2
1
Adder/Subtractor
Stratix II Device Handbook, Volume 1
Saturate
Saturate
Multipliers Together
Round/
Round/
Q1.15
Q1.15
Summation Stage
for Adding Four
Summation
Block
Adder
Interconnect
to MultiTrack
Multiplexer
Selection
Output
Stratix II Architecture
ENA
D
CLRN
Q
2–43