EP1S25F1020I6N Altera, EP1S25F1020I6N Datasheet - Page 96

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EP1S25F1020I6N

Manufacturer Part Number
EP1S25F1020I6N
Description
IC STRATIX FPGA 25K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S25F1020I6N

Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
706
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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PLLs & Clock Networks
2–82
Stratix Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
Table 2–18. Stratix Device PLL Availability
Device
PLLs 5 and 6 each have eight single-ended outputs or four differential outputs.
PLLs 11 and 12 each have one single-ended output.
EP1S30 and EP1S40 devices do not support these PLLs in the 780-pin FineLine BGA
Table
v
v
v
v
v
v
v
2–18:
1
v
v
v
v
v
v
v
2
provide general purpose clocking with multiplication and phase shifting
as well as high-speed outputs for high-speed differential I/O support.
Enhanced and fast PLLs work together with the Stratix high-speed I/O
and advanced clock architecture to provide significant improvements in
system performance and bandwidth.
The Quartus II software enables the PLLs and their features without
requiring any external devices.
each Stratix device.
v
v
v
v
v
v
v
3
v
v
v
v
v
v
v
4
Fast PLLs
v
v
v
v
7
(3)
(3)
v
v
v
v
8
(3)
(3)
v
v
v
v
Table 2–18
9
(3)
(3)
v
v
v
v
10
(3)
(3)
shows the PLLs available for
5(1)
v
v
v
v
v
v
v
®
package.
Enhanced PLLs
6(1)
v
v
v
v
v
v
v
Altera Corporation
v(3) v(3)
11(2) 12(2)
v
v
July 2005
v
v

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