EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 6

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Page 6
Quartus II Mapping Issue with PCI Express (PCIe) Interfaces Using the
Hard IP Block
High I/O Pin Leakage Current
Table 4. I/O Pin Leakage Current for Arria II GX ES Devices
Errata Sheet for Arria II GX Devices
Symbol
I
OZ
I
I
f
Tri-stated I/O Pin
Description
Input pin
If any invalid DLL configuration critical warning appears after recompilation in the
Quartus II software version 10.0 SP1 and later, as shown in
regenerate the megafunction or the IP core and recompile the design.
Example 1.
Critical Warning: DLL atom
“ddr2_230:ddr2_230_inst|ddr2_230_controller_phy:ddr2_230_controller_phy_inst|d
dr2_230_phy:ddr2_230_phy_inst|ddr2_230_phy_alt_mem_phy:ddr2_230_phy_alt_m
em_phy_inst|ddr2_230_phy_alt_mem_phy_clk_reset:clk|dll” is using a clock period
of 4.35 ns, which is outside the valid range for its configuration mode. When the delay
buffer mode is “LOW” and the delay chain length is "8", the valid range is from 4.55 ns
to 5.88 ns.
The Quartus II software versions 9.1, 9.1 SP1, and 9.1 SP2 incorrectly allow logical
channel 0 to be placed in any physical channel for ×1 and ×4 PCIe Gen1 interfaces
with the hard IP block. For correct operation with the hard IP block, logical channel 0
must be placed in physical channel 0.
This issue is fixed in the Quartus II software version 10.0; however, Altera
recommends upgrading to the Quartus II software version 10.0 SP1. If you have
already designed or fabricated your boards using the incorrect mapping, file a service
request using
I/O pins on ES devices have a higher leakage current than what is specified in the
Arria II GX Data Sheet version 1.2. For Arria II GX ES device I/O pin leakage current
for all I/O pins, refer to
All Arria II GX production devices will have a lower leakage current. For production
device specifications, refer to the
the Arria II GX Device Handbook.
Invalid DLL Configuration Critical Warning
mysupport.altera.com
V
V
O
I
= 0V to V
= 0V to V
Conditions
Quartus II Mapping Issue with PCI Express (PCIe) Interfaces Using the Hard IP Block
Table
CCIOMAX
CCIOMAX
4.
Device Datasheet for Arria II GX Devices
for assistance to remedy this problem.
Min
-80
-80
Type
—
—
Example
February 2011 Altera Corporation
Max
80
80
1, you must
in volume 3 of
Unit
μA
μA