EP2SGX60EF1152I4N Altera, EP2SGX60EF1152I4N Datasheet - Page 4
EP2SGX60EF1152I4N
Manufacturer Part Number
EP2SGX60EF1152I4N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152I4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2187
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152I4N
Manufacturer:
ALTERA
Quantity:
534
- Current page: 4 of 316
- Download datasheet (2Mb)
Features
1–2
Stratix II GX Device Handbook, Volume 1
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Transceiver block features:
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Support for multiple intellectual property megafunctions from
Altera
Program (AMPP
Support for design security using configuration bitstream
encryption
Support for remote configuration updates
High-speed serial transceiver channels with clock data recovery
(CDR) provide 600-megabits per second (Mbps) to 6.375-Gbps
full-duplex transceiver operation per channel
Devices available with 4, 8, 12, 16, or 20 high-speed serial
transceiver channels providing up to 255 Gbps of serial
bandwidth (full duplex)
Dynamically programmable voltage output differential (V
and pre-emphasis settings for improved signal integrity
Support for CDR-based serial protocols, including PCI Express,
Gigabit Ethernet, SDI, Altera’s SerialLite II, XAUI, CEI-6G,
CPRI, Serial RapidIO, SONET/SDH
Dynamic reconfiguration of transceiver channels to switch
between multiple protocols and data rates
Individual transmitter and receiver channel power-down
capability for reduced power consumption during
non-operation
Adaptive equalization (AEQ) capability at the receiver to
compensate for changing link characteristics
Selectable on-chip termination resistors (100, 120, or 150 Ω) for
improved signal integrity on a variety of transmission media
Programmable transceiver-to-FPGA interface with support for
8-, 10-, 16-, 20-, 32-, and 40-bit wide data transfer
1.2- and 1.5-V pseudo current mode logic (PCML) for 600 Mbps
to 6.375 Gbps (AC coupling)
Receiver indicator for loss of signal (available only in PIPE
mode)
Built-in self test (BIST)
Hot socketing for hot plug-in or hot swap and power
sequencing support without the use of external devices
Rate matcher, byte-reordering, bit-reordering, pattern detector,
and word aligner support programmable patterns
Dedicated circuitry that is compliant with PIPE, XAUI, and
GIGE
Built-in byte ordering so that a frame or packet always starts in
a known byte lane
Transmitters with two PLL inputs for each transceiver block
with independent clock dividers to provide varying clock rates
on each of its transmitters
®
MegaCore
SM
®
) megafunctions
functions and Altera Megafunction Partners
Altera Corporation
October 2007
OD
)
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