EP1SGX25FF1020I6N Altera, EP1SGX25FF1020I6N Datasheet - Page 171
EP1SGX25FF1020I6N
Manufacturer Part Number
EP1SGX25FF1020I6N
Description
IC STRATIX GX FPGA 25K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX25FF1020I6N
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
607
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1SGX25FF1020I6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 4–65. Input Timing Diagram in DDR Mode
Altera Corporation
February 2005
Input To
Logic Array
Data at
input pin
CLK
A'
B'
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from LEs on rising clock edges. These
output registers are multiplexed by the clock to drive the output pin at a
×
while the other output register clocks the second bit out on the clock low
time.
shows the DDR output timing diagram.
2 rate. One output register clocks the first bit out on the clock high time,
A0
Figure 4–66
B1
A1
B2
shows the IOE configured for DDR output.
A1
B1
A2
B3
A2
B2
A3
Stratix GX Device Handbook, Volume 1
B4
A3
B3
Stratix GX Architecture
Figure 4–67
4–105
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