EP2AGX190EF29I5N Altera, EP2AGX190EF29I5N Datasheet - Page 58

• Manufacturer Part Number: EP2AGX190EF29I5N
• Description: IC ARRIA II GX FPGA 190K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190EF29I5N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–50
Table 1–40. Transceiver Block AC Specifications for Arria II GX Devices
Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Sinusoidal jitter
tolerance at
3072 Mbps
Notes to
(1) Dedicated refclk pins are used to drive the input reference clocks. The jitter numbers are valid for the stated conditions only.
(2) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
(3) The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.
(4) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(5) The jitter numbers for PCIe are compliant to the PCIe Base Specification 2.0.
(6) The jitter numbers for Serial RapidIO
(7) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(8) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.
(9) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
(10) The Fibre Channel transmitter jitter generation numbers are compliant to the specification at the 
(11) The Fibre Channel receiver jitter tolerance numbers are compliant to the specification at the 
(12) Arria II PCIe receivers are compliant to this specification provided the VTX_CM-DC-ACTIVEIDLE-DELTA of the upstream transmitter is less than 50 mV.
(13) The jitter numbers for Serial Advanced Technology Attachment (SATA) are compliant to the Serial ATA Revision 3.0 Specification.
(14) The jitter numbers for Common Public Radio Interface (CPRI) are compliant to the CPRI Specification V3.0.
(15) The jitter numbers for Open Base Station Architecture Initiative (OBSAI) are compliant to the OBSAI RP3 Specification V4.1.
SONET/SDH Transmit Jitter Generation
Peak-to-peak jitter at
622.08 Mbps
RMS jitter at 622.08 Mbps
Peak-to-peak jitter at
2488.32 Mbps
RMS jitter at 2488.32 Mbps
Description
Symbol/
Table
Description
Symbol/
1–40:
1843.2 KHz to
frequency =
frequency =
Conditions
Pattern =
Pattern =
21.8 KHz
Table 1–41
Arria II GZ devices.
20 MHz
CJPAT
CJPAT
Jitter
Jitter
Pattern = PRBS15
Pattern = PRBS15
Pattern = PRBS15
Pattern = PRBS15
®
lists the transceiver jitter specifications for all supported protocols for
are compliant to the RapidIO Specification 1.3.
Min
Conditions
(3)
> 8.5
> 0.1
Typ
I3
Max
Min
—
—
—
—
Min
–C3 and –I3
> 8.5
> 0.1
Typ
C4
Typ
—
—
—
—
(Note 1)
Max
(Note
Max
0.01
0.01
0.1
0.1
Chapter 1: Device Datasheet for Arria II Devices
R
Min
1),
interpretability point.
(Part 13 of 13)
T
inter operability point.
(2)
Min
C5, I5
—
—
—
—
Typ
> 8.5
> 0.1
(Part 1 of 8)
December 2010 Altera Corporation
–C4 and –I4
Max
Typ
—
—
—
—
Switching Characteristics
Min
0.01
0.01
Max
0.1
0.1
Typ
> 8.5
> 0.1
C6
Unit
UI
UI
UI
UI
Max
Unit
UI
UI