EP1S30B956C5 Altera, EP1S30B956C5 Datasheet - Page 127

• Manufacturer Part Number: EP1S30B956C5
• Description: IC STRATIX FPGA 30K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S30B956C5

• Number Of Logic Elements/cells: 32470
• Number Of Labs/clbs: 3247
• Total Ram Bits: 3317184
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Figure 2–66. Input Timing Diagram in DDR Mode
Altera Corporation
July 2005
Input To
Logic Array
Data at
input pin
CLK
A'
B'
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from LEs on rising clock edges. These
output registers are multiplexed by the clock to drive the output pin at a
×2 rate. One output register clocks the first bit out on the clock high time,
while the other output register clocks the second bit out on the clock low
time.
shows the DDR output timing diagram.
A0
Figure 2–67
B1
A1
B2
shows the IOE configured for DDR output.
A1
B1
A2
B3
A2
B2
A3
B4
A3
B3
Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–68
2–113